While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. Communication to the device can be paused via the hold pin (HOLD). Access to the device is controlled through a Chip Select (CS) input. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The 25LC256-I/P is a 256 Kb Serial EEPROM utilizing the industry standard Serial Peripheral Interface (SPI) compatible serial bus. SCHEMATIC & PRINTED CIRCUIT BOARD DESIGN.
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